1. Technical Field
The embodiments described herein are related to a semiconductor memory apparatus, in particular, to an address replacing circuit and a semiconductor memory apparatus having the same.
2. Related Art
A conventional semiconductor memory apparatus selects a word line designated by a row address and activates corresponding memory cells. The semiconductor memory apparatus activates a column selection signal designated by a column address and performs a data input/output operation on corresponding memory cells. During an active operation of the semiconductor memory apparatus, one of a plurality of memory banks is activated, and one column selection signal designed by a column address is enabled.
As such, the semiconductor memory apparatus includes a row decoder that selects a word line according to a row address, and a column decoder that enables a column selection signal according to a column address.
In the general semiconductor memory apparatus, the number of row addresses is determined according to the international standard, which is defined by JEDEC (Joint Electron Device Engineering Council). The international standard defines the number of row addresses according to a capacity of the semiconductor memory apparatus and the amount of data input/output at a time. For example, in the case of a semiconductor memory apparatus (hereinafter, referred to as X32 semiconductor memory apparatus) in which a capacity is 1 GByte and the amount of data input/output at a time is 32, the number of row addresses is set to 13. In this case, in the case where a fourteenth row address needs to be used, one bit of a column address is additionally used to replace a function of the fourteenth row address, in the conventional semiconductor memory apparatus. However, according to this technology, unnecessary bit lines are activated, thereby causing a power loss.
In addition, in the case where two semiconductor memory apparatuses, each having a small capacity, are juxtaposed to implement a semiconductor memory apparatus having a large capacity, the number of row addresses, which is defined by the international standard, is different for each semiconductor memory apparatus. Therefore, this technology cannot be used. For example, it is assumed that two semiconductor memory apparatuses (hereinafter, referred to as X8 semiconductor memory apparatus), where a capacity is 512 MByte and the amount of data input/output at a time is 8, are used to implement one semiconductor memory apparatus (hereinafter, referred to as X16 semiconductor memory apparatus), in which a capacity is 1 GByte and the amount of data input/output at a time is 16. In this case, the X8 semiconductor memory apparatus uses 13 row addresses and the X16 semiconductor memory apparatus uses 14 row addresses. Therefore, there occurs a problem when using addresses.
As such, in a conventional semiconductor memory apparatus, it is difficult to effectively use the row addresses because of the standard specifications, which are defined according to the capacity and the amount of data input/output at a time. For this reason, there is a limitation in juxtaposing semiconductor memory apparatus each having a small capacity to implement a semiconductor memory apparatus having a large capacity. In addition, a large amount of time and cost are consumed in manufacturing the semiconductor memory apparatus.